The present invention relates to improvements in programmable logic devices (PLDs), and more particularly to techniques for limiting the sense currents drawn during interrogation of the PLD array and reducing the noise coupling onto the array sense amplifiers caused by the switching of cell selection devices.
The architecture of the typical PLD allows the buffered input signals to pass directly into the programmable AND array or matrix of the device. For example, a PLD may have sixteen input signals making up thirty-two possible input lines, since each input signal normally has true and compliment signals associated therewith going to the AND array.
Each AND array comprises a plurality of memory cells or switches, arranged in an array (the AND array) of rows and columns (or product terms). The input signals drive respective rows of the array, and the respective product terms are connected to sense amplifiers, an OR gate array and other output logic circuitry as is known to those skilled in the art. The state of a particular array cell determines whether or not the respective row input signal is coupled onto the corresponding product term line for that memory cell.
The memory cells each typically comprise a select transistor which is turned on when the corresponding row input signal is active. If the cell memory unit (a fuse switch or other memory device such as a floating-gate field effect transistor) is conductive, the input signal will be coupled onto the product term.
The assignee of the invention has recently developed a PLD employing electrically-erasable, floating-gate, field effect transistors as the memory or sense element of the cells of the AND array. Such floating gate transistors have been employed in the past for electrically erasable, programmable memories (EEPROMs). In a typical EEPROM memory, the select transistor for a particular cell is formed by the intersection of a polysilicon input line and the product term active area. The polysilicon acts as the gate electrode of the select transistor, with the source and drain formed by N-type implanted dopant in the active area. During processing of the PLD, the N-type dopant laterally diffuses beneath the polysilicon gate. This lateral diffusion forms an overlap region associated with the gate. This capacitance is often referred to as Miller capacitance.
A conventional electrically erasable memory array is illustrated by the simplified diagram of FIG. 1. Traditionally, the select transistor M1 is placed between the sense transistor M2 (the floating gate device) and the sense amplifier located at the end of the column or product term. This configuration works well for memory applications where only one row switches at a time. This configuration also lays out in the minimum chip area because the column can be bi-directional, i.e., used for both reading and writing data from and to the memory array. The conventional EEPROM cell configuration is not advantageous for a PLD, because many rows may be switching simultaneously, leading to increased product term noise due to capacitive coupling of the overlap region, increasing input-to-output signal delays. With sixteen (or more) input lines switching from high to low (or vice versa) simultaneously, considerable switching noise can be capacitively coupled onto the product term. Product term noise can result in debiasing of the high speed sense amplifier, causing increased input-to-output signal delays.
Another characteristic of PLDs is the relatively high cell currents that may be drawn through a particular product term when several of the row lines are selected and the memory cells associated with those row lines are conductive.
In the PLD configuration recently developed by the assignee of the present invention, separate sense amplifiers are provided for each product term, and function as current sensing voltage sources. The advantage of this sense amplifier is its high speed. In order to provide the required high speed, the sense amplifiers are very sensitive, and are activated by relatively small input voltage swings. The amplifiers function in an analogous manner to a voltage source which can source a high current level to maintain the voltage level. The sense amplifier sources current to ground through the memory cells which are turned on. Thus, for an array with 32 rows of cells arranged in columns or product terms, when many cells are turned on the sense amplifier for a particular product term may be sourcing many times the current required for a single cell. For example, each programmed cell may be capable of sinking 50 .mu.A each, and it is possible (although not probable) that one-half of the cells in a 2048 cell array could be on, sinking 50 .mu.A each for a total of 51.2 mA of cell current. The high current flow leads to excessive power dissipation and chip failure rates, and is unnecessary because current flow through only one cell of a product term is really needed for sense amplifier operation.
It is therefore an object of the present invention to provide means for isolating the product term sense amplifiers of a PLD from row switching noise.
A further object is to provide an improved PLD with limited sense currents and very high input-to-output signal speeds.